1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to reduce the burden in designing photomasks and to increase depth of focus.
2. Description of the Related Art
As the packing density of integrated circuits has increased in recent years, so too has the requirement for semiconductor device manufacturing equipment to achieve smaller feature size—patterns that contain lines whose width is shorter than the wavelength of exposure light employed in the manufacturing process. Along with this trend, selection of masks that can produce fine, high-resolution patterns has been conducted, and phase shift masks such as halftone masks are increasingly used in the lithography technology. The halftone masks are advantageous in improving resolution, but attention needs to be paid to the fact that they may create side lobes (sub-peaks) around a primary feature. To avoid this, a means of preventing the generation of side lobes has conventionally been provided on the mask.
An example of the foregoing means provided on the mask includes for instance a method by which the generation of side lobes is prevented by arranging Cr patterns on areas where side lobes are likely to appear. While this method can successfully prevent the generation of side lobes, it involves the use of a tri-tone mask of three layers owing to the presence of the Cr patterns arranged over the mask, placing a burden on the mask manufacture and defect inspection of masks.
In response to the demand for finer patterns, sub-resolution assist features (SRAF), which are not meant to print, are now increasingly placed over the reticle in order primarily to increase depth of focus. This SRAF technology, however, is one wherein assist features should not be printed on the surface of the resist and hence the assist features are arranged in the reticle in such size that they do not print. For this reason, there is a limitation to a further improvement of depth of focus by simply arranging relatively large SRAFs, limiting the use of larger SRAFs.
Examples of pattern layouts for semiconductor devices are those containing both repetitive patterns of a particular cell layout as typified by memory devices and a variety of randomly arranged patterns as typified by LOGIC LSIs. In many cases the memory cell layout is designed using the values that are most critical in the design rules of the corresponding generation. One of the lithography-associated resolution enhancement technologies for accomplishing the foregoing is the method that uses a phase shift mask, which is mainly used for the formation of critical layers. In this regard, masks for a metal interconnection layer (holes/trenches) are those with less features (openings).
Here, FIG. 10 shows a schematic view of a reduction projection exposure device, and FIGS. 11A to 11C show sections of general photomasks of various types that are used upon manufacture of a semiconductor device.
The reduction projection exposure device shown in FIG. 10 includes an illumination light source 101, an illumination optical system 104 for guiding light from the illumination light source 101 to a reticle 103 (photomask) placed on a reticle stage 102, and a projection optical system, which is a reduction projection lens 105. The illumination optical system 104 includes an elliptic mirror 110, a fly eye lens 111, and an aperture diaphragm 112. Light from the illumination light source 101 is guided to the reticle 103 through the illumination optical system 104, and the pattern on the reticle 103 is projected onto the resist layer on a wafer through the reduction projection lens 105. Note that in exposure devices using excimer lasers as a light source, the elliptic mirror 110 is not provided, and the illumination light source 101 serves as a laser beam source.
A mask 102 shown in FIG. 11A is a chrome mask that is also referred to as a binary mask, in which a metal masking film 122 such as Cr patterns is formed over a quarts dry plate 121. Using a reduction projection exposure device like that shown in FIG. 10, a pattern is projected onto a wafer 106 by means of light passing through Cr-free areas of the mask 120. A mask 130 shown in FIG. 11B is a halftone phase shift mask having semi-transparent metallic thin film patterns 132 made primarily of MoSi or the like provided over a quarts dry plate 131. A mask 140 shown in FIG. 11C is a Levenson phase shift mask that is identical to the chrome mask (mask 120) shown in FIG. 11A except that a trench 141 is formed that produces 180 degree phase shift in particular light passing through the quarts dry plate 121.
FIG. 12 shows a light intensity distribution obtained when the wafer is exposed using the chrome mask (mask 120) shown in FIG. 11A, and FIG. 13 shows a light intensity distribution obtained when the wafer is exposed using the halftone phase shift mask (mask 130) shown in FIG. 11B. A comparison between the light intensity distributions of FIGS. 12 and 13 reveals the differences in light intensity between different masks. Referring specifically to FIG. 13, relatively small positive peaks are seen at either side of the main positive peak for the feature 133; these small peaks are the essential cause of side lobes that are specific to halftone phase shift masks.
An example of how side lobes are created in the resist pattern will be described below. FIG. 14A is a top view of a mask pattern 150 used upon production a seal ring that is used for preventing the entry of moisture into freshly prepared LSI chips from the outside. The seal ring is also referred to as a moisture resistance ring. FIG. 14B is an image view of a resist pattern formed using the mask pattern 150. It is evident that there are side lobes S generated in areas other than the desired pattern 150 of FIG. 14B, which are not present in the mask pattern 150 of FIG. 14A. The presence of side lobes S in the resist upon exposure of the wafer results in resist pattern collapse, printing of the side lobes S after etching, etc., leading to poor device quality. Thus, there has been a need to perform a resist exposure process while avoiding the creation of such side lobes. Note that even when the primary feature has the same shape as the seal ring, similar side lobe-related problems occur. Thus it has been required to pay attention when attempting to achieve linewidths of about more than three times as large as the minimal linewidths of the corresponding generation, depending on the setting of mask bias at the standard exposure dose, though.
FIG. 15A shows an example of a mask layout for hole pattern, which is provided with SRAFs that have become frequently used. As shown in FIG. 15A, assist features 161 are arranged around a primary feature 160 in such a way that they assist exposure through the primary feature 160. It has been shown that this mask layout can increase depth of focus (DOF). The size and position of the SRAFs are determined in light of the conditions of the resist exposure process; however, it is generally important to ensure that SRAFs never print. Accordingly, although DOF is nearly proportional to the size of a SRAF, SRAFs need to be used in such a way that they never print on the resist, and therefore, there is an upper limit with respect to their operable size. If the size of SRAF exceeds this upper limit, it results in the formation of unwanted features 163, which are derived from the assist patterns 161, at positions other than the primary feature 160, as shown in FIG. 15B.
To overcome this problem the following method has been proposed, for example, which comprises the steps of printing a photomask pattern onto a photosensitive resin film, generating an acid in the photosensitive resin film, forming a crosslinkable material-containing resin film over the photosensitive resin film, and subjecting both of the resin films to heat treatment to allow the crosslinkable material to undergo crosslinking to form a reaction layer at their interface, whereby printed unwanted features are eliminated from the printed features (see Japanese Patent Application Laid-Open No. 2001-005197). This method is, however, limited to chemically amplified resists in terms of applicable resists, and thus the range of selection of available of resist materials is narrow. In addition, crosslinking reactions in the crosslinkable material-containing resin film are difficult to control. Thus, with this method, unwanted features of varying sizes cannot necessarily be removed successfully independent of the types of resist materials.
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to thereby reduce the burden in designing photomasks and to increase depth of focus.